Gate cut on a vertical field effect transistor with a defined-width inorganic mask

A method of cutting a gate on a vertical field effect transistor (VFET), comprising:

• depositing a memorization layer onto the VFET around a spacer on a sidewall of the field effect transistor;
• patterning a planarizing layer onto the memorization layer;
• patterning an anti-reflective coating layer onto the planarizing layer;
• patterning a photoresist layer onto the anti-reflective coating on ends of fins extending from a substrate in the VFET, wherein the planarizing layer, the anti-reflective coating layer, and the photoresist form a mask;
• etching the anti-reflective coating layer portion of the mask from the VFET;
• arc etching the planarizing layer and the photoresist layer portions of the mask from VFET;
• pulling down the spacer forming a void between gates on the VFET and exposing a hard mask on the fins;
• reactive ion etching the hard mask by pulling down on the hard mask and reactive ion etching vertically around the gates to form gates with a defined width mask;
• and
• removing the memorization layer from the VFET.