# US 2018/0006145 A1 · Power mosfet with metal filled deep sinker contact for csp

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0006145 A1
- Document ID: US20180006145A1
- Status: Published application
- Kind: A1
- Application number: 15/342,896
- Filed: 2016-11-03
- Published: 2018-01-04
- Earliest claimed: 2016-06-30
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Yufei XIONG; Yunlong LIU; Hong YANG; Ho LIN; Tian Ping LV; Sheng ZOU; Qiu Ling JIA
- Web page: https://patentgrep.com/patent/US20180006145A1

## CPC

- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10P 14/40: of conductive or resistive materials
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 12/491: {having both emitter contacts and collector contacts in the same substrate side}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/115: {Resistive field plates, e.g. semi-insulating field plates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

## Claims

### Claim 1

A method of forming an integrated circuit (IC) including a power semiconductor device, comprising:
providing a substrate having an epitaxial (epi) layer thereon with at least one transistor formed including within said epi layer and being covered by a pre-metal dielectric (PMD) layer;
etching contact openings through said PMD layer and at least a portion of said epi layer, said contact openings including a sinker trench which extends to at least a first node of said power semiconductor device;
depositing a metal fill material, wherein said metal fill material covers a sidewall and a bottom of said sinker trench but does not completely fill said sinker trench;
depositing a dielectric filler layer over said metal fill material to fill said sinker trench;
removing an overburden region of said dielectric filler layer stopping on a surface of said metal fill material in said overburden region to form a sinker contact, wherein a portion of said dielectric filler layer remains in said sinker trench after said removing of said overburden region of said dielectric filler layer; and
forming a patterned interconnect metal to provide a connection between said interconnect metal and said metal fill material on said sidewall of said sinker trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein said depositing said metal fill material comprises chemical vapor depositing (CVD) of tungsten (W).

### Claim 3 (depends on 1)

The method of claim 1, wherein said depositing said dielectric filler layer comprises spin on glass (SOG) coating.

### Claim 4 (depends on 1)

The method of claim 1, wherein said removing said overburden region of said dielectric filler layer comprises chemical mechanical polishing (CMP).

### Claim 5 (depends on 1)

The method of claim 1, wherein said epi layer is at least 5 μm thick, and said sinker trench reaches an interface between said epi layer and said substrate.

### Claim 6 (depends on 1)

The method of claim 1, wherein said power semiconductor device comprises a metal-oxide-semiconductor field effect transistor (MOSFET) device, and wherein said first node comprises a drain.

### Claim 7 (depends on 1)

The method of claim 1, wherein said power semiconductor device comprises a bipolar device, and wherein said first node comprises a collector.

### Claim 8 (depends on 1)

The method of claim 1, wherein a doping level in said epi layer is at least one order of magnitude less than a doping level in said substrate, and said sinker contact extends into said substrate.

### Claim 9 (depends on 1)

The method of claim 1, further comprising forming a barrier metal liner in said sinker trench before said depositing said metal fill material.

### Claim 10

A power semiconductor device, comprising
a substrate having an epitaxial (epi) layer thereon;
a first device terminal, a second device terminal within a well, and a third device terminal comprising one of a buried drain and a buried collector;
a sinker contact comprising a filled sinker trench extending through a pre-metal dielectric layer and at least a portion of said epi layer to said third device terminal, wherein said sinker contact comprises a metal fill material that covers a sidewall and a bottom of said sinker trench but does not completely fill said sinker trench, and an inner dielectric filler layer disposed inside said metal fill material for filling said sinker trench so that at least a portion of said metal fill material is disposed between said sidewall and said inner dielectric filler layer.

### Claim 11 (depends on 10)

The power semiconductor device of claim 10, wherein said metal fill material comprises tungsten (W).

### Claim 12 (depends on 10)

The power semiconductor device of claim 10, wherein said dielectric filler layer comprises a sintered spin on glass (SOG) coating that has micro-porosity.

### Claim 13 (depends on 10)

The power semiconductor device of claim 10, wherein said epi layer is at least 5 μm thick, and wherein said sinker trench reaches an interface between said epi layer and said substrate.

### Claim 14 (depends on 10)

The power semiconductor device of claim 10, wherein said power semiconductor device comprises a metal-oxide-semiconductor field effect transistor (MOSFET) device, and wherein said third device terminal comprises said buried drain.

### Claim 15 (depends on 10)

The power semiconductor device of claim 10, wherein said power semiconductor device comprises a bipolar device, and wherein said third device terminal comprises said buried collector.

### Claim 16

An integrated circuit (IC) including a power semiconductor device, comprising:
a substrate having an epitaxial (epi) layer thereon;
said power semiconductor device including:
a first device terminal, a second device terminal within a well, and a third device terminal comprising one of a buried drain and a buried collector;
a sinker contact comprising a filled sinker trench extending through a pre-metal dielectric layer and at least a portion of said epi layer to said third device terminal, wherein said sinker contact comprises a metal fill material comprising tungsten (W) that covers a sidewall and a bottom of said sinker trench but does not completely fill said sinker trench, and an inner dielectric filler layer inside said metal fill material for filling said sinker trench so that at least a portion of said metal fill material is disposed between said sidewall and said inner dielectric filler layer.

### Claim 17 (depends on 16)

The IC of claim 16, wherein a dielectric filler layer comprises a sintered spin on glass (SOG) coating that has micro-porosity.

### Claim 18 (depends on 16)

The IC of claim 16, wherein said epi layer is at least 5 μm thick, and said sinker trench reaches an interface between said epi layer and substrate.

### Claim 19 (depends on 16)

The IC of claim 16, wherein said power semiconductor device comprises a metal-oxide-semiconductor field effect transistor (MOSFET) device, and wherein said third device terminal comprises said buried drain.

### Claim 20 (depends on 16)

The IC of claim 16, wherein said power semiconductor device comprises a bipolar device, and wherein said third device terminal comprises a collector.