Array substrate, fabrication method, and display panel

A fabrication method for the array substrate, comprising:

• providing a substrate;
• and
• forming at least one thin-film-transistor on the substrate, wherein forming the at least one thin-film-transistor on the substrate includes:
• forming an active layer on the substrate, including a source region, a drain region, and a channel region located between the source region and the drain region;
• forming a source electrode metal contact layer, a drain electrode metal contact layer, and a barrier layer on a side of the active layer facing away from the substrate, wherein:
• the source electrode metal contact layer, the drain electrode contact layer, and the barrier layer are coplanar with each other;
• the source electrode metal contact layer has an orthogonal projection on the active layer overlapping with the source region;
• the drain electrode metal contact layer has an orthogonal projection on the active layer overlapping with the drain electrode;
• and
• the barrier layer is located between the source electrode metal contact layer and the drain electrode metal contact layer, and has an orthogonal projection on the active layer overlapping with the channel region;
• and
• forming a source electrode on a side of the source electrode metal contact layer facing away from the active layer, forming a drain electrode on a side of the drain electrode metal contact layer facing away from the active layer, and forming a gate electrode on a side of the barrier layer facing away from the active layer, wherein:
• the source electrode is electrically connected to the source region in the active layer through the source electrode metal contact layer;
• and
• the drain electrode is electrically connected to the drain region in the active layer through the drain electrode metal contact layer.

A display panel, comprising an array substrate, wherein the array substrate includes:

• a substrate;
• and
• a plurality of thin-film-transistors, wherein, the thin-film-transistor includes:
• an active layer formed on the substrate, including a source region, a drain region, and a channel region located between the source region and the drain region;
• a source electrode metal contact layer, a drain electrode metal contact layer, and a barrier layer formed on a side of the active layer facing away from the substrate, wherein:
• the source electrode metal contact layer, the drain electrode metal contact layer, and the barrier layer are different regions of a same layer;
• the source electrode metal contact layer has an orthogonal projection on the active layer overlapping with the source region;
• the drain electrode metal contact layer has an orthogonal projection on the active layer overlapping with the drain electrode;
• and
• the barrier layer is located between the source electrode metal contact layer and the drain electrode metal contact layer, and has an orthogonal projection on the active layer overlapping with the channel region;
• and
• a source electrode formed on a side of the source electrode metal contact layer facing away from active layer, a drain electrode formed on a side of the drain electrode metal contact layer facing away from the active layer, and a gate electrode insulated from the barrier layer and formed on a side of the barrier layer facing away from the active layer, wherein:
• the source electrode is electrically connected to the source region in the active layer through the source electrode metal contact layer;
• and
• the drain electrode is electrically connected to the drain region in the active layer through the drain electrode metal contact layer.