Epi integrality on source/drain region of finfet

A method for manufacturing a semiconductor device, the method comprising:

• providing a substrate structure including a substrate, at least one semiconductor fin on the substrate, and a trench isolation structure surrounding and laterally abutting the semiconductor fin and having an upper surface flush with an upper surface of the semiconductor fin, the trench isolation structure comprising a first trench isolation portion and a second trench isolation portion disposed on opposite sides of the semiconductor fin along a first direction parallel to a longitudinal direction of the semiconductor fin, and a third trench isolation portion and a fourth trench isolation portion on distal ends of the semiconductor fin along a second direction intersecting the first direction;
• forming a patterned first hardmask layer having an opening on the substrate structure, the opening exposing an upper surface of the third and fourth trench isolation portions;
• forming a first insulator layer filling the opening to form an insulating portion including a portion of the first insulator layer in the opening and a portion of the trench isolation structure below the portion of the first insulator layer in the opening;
• removing the patterned first hardmask layer exposing a portion of the semiconductor fin below the patterned first hardmask layer and the upper surface of the trench isolation structure;
• and
• removing a portion of the first insulator layer and a portion of the exposed trench isolation structure such that an upper surface of the first and second trench isolation portions is lower than the upper surface of the semiconductor fin to expose an upper portion of the semiconductor fin and an upper portion of the insulating portion.