Back to results
US 2018/0006128 A1Published application
Method and structure for forming mosfet with reduced parasitic capacitance
AssigneeInternational Business Machines Corporation
InventorsKangguo CHENG, Peng Xu, Chen Zhang
Life of this patent
Estimating the term…
Abstract
A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material.
Claims22
A method of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), said method comprising:
- on a gate structure a gate contact metal structure coated with a high-k sidewall spacer film, etching off an upper portion of said high-k sidewall spacer film from vertical walls of said gate structure, leaving in place a lower portion of said high-k sidewall spacer film;
- replacing at least a portion of said etched-off upper portion of high-k sidewall spacer film on said vertical walls with an ultra low-k material;
- depositing a layer of metal to serve as a source contact metal or as a drain contact metal such that a first side surface of said ultra low-k material directly contacts a first side surface of the gate contact metal and a second side surface of said ultra low-k material directly contacts a side surface of one of said source contact metal or said drain contact metal;
- and
- polishing a top surface of the MOSFET until the second side surface of the ultra low-k material directly contacts along an entirety of a vertical dimension of the side surface of the source contact metal layer or the drain contact metal layer,
- wherein a thickness of the upper portion of ultra low-k sidewall spacer film is approximately the same as a thickness of the lower portion of high-k sidewall spacer film.
3 more elements
A finFET (fin Field Effect Transistor) comprising:
- a gate structure comprising a gate contact covering a high impedance film layer;
- a fin channel directly under said gate structure such that a movement of carriers is controlled by a voltage in said gate contact;
- a source epitaxial region covered by a source contact metal layer, adjacent to a first side of said gate structure;
- and
- a drain epitaxial region covered by a drain contact metal layer, adjacent to a second side of said gate structure and opposing said first side,
- wherein said gate structure further comprises a gate sidewall spacer layer, comprising an upper portion and a lower portion, to isolate said gate from said source contact metal layer and said drain contact metal layer,
- wherein said lower portion of said gate sidewall spacer layer comprises a material having a high-k value and said upper portion of said gate sidewall spacer layer comprises a material having an ultra low-k material and a first side surface of the ultra low-k material directly contacts a side surface of a metal layer comprising said gate contact and a second side surface of the ultra low-k material directly contacts one of a side surface of the source contact metal layer or a side surface of the drain contact metal layer along an entirety of a vertical dimension of the side surface of the source contact metal layer or the drain contact metal layer, and
- wherein a thickness of the upper portion is approximately the same as a thickness of the lower portion.
5 more elements
(canceled)
(canceled)
A MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) comprising:
- a gate structure comprising a gate contact covering a high impedance film layer;
- a channel directly under said gate structure such that a movement of carriers is controlled by a voltage in said gate contact;
- a source epitaxial region covered by a source contact metal layer, adjacent to a first side of said gate structure;
- and
- a drain epitaxial region covered by a drain contact metal layer, adjacent to a second side of said gate structure and opposing said first side,
- wherein said gate structure further comprises a gate sidewall spacer layer to isolate said gate from said source contact metal layer and from said drain contact metal layer,
- wherein said gate sidewall spacer layer comprises an upper portion and a lower portion between said gate structure and said drain contact metal layer and between said gate structure and said source contact metal layer,
- wherein the upper portion comprises a material having an ultra low-k material, and a first side surface of the ultra low-k material directly contacts a first side surface of a metal comprising said gate contact and a second side surface of the ultra low-k material directly contacts a side surface of one of the source contact metal layer and the drain contact metal layer along an entirety of a vertical dimension of the side surface of the source contact metal layer or the drain contact metal layer, and wherein a thickness of the upper portion is approximately the same as a thickness of the lower portion.
5 more elements
(canceled)
Dependencies are inferred from the claim text.