Mos-varactor design to improve tuning efficiency
AssigneesSemiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
InventorYONG LI
Life of this patent
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Abstract
A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer, and a metal gate on the N-type work function adjustment layer. The P-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. The gate stack structure in the MOS varactor can increase the tuning range of the MOS varactor.
Claims20
A gate stack structure for a MOS varactor, comprising:
- a substrate including a channel region;
- a high-k dielectric layer on the channel region of the substrate;
- a P-type work function adjustment layer on the high-k dielectric layer, the P-type work function adjustment layer including a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion;
- an N-type work function adjustment layer on the P-type work function adjustment layer;
- and
- a metal gate on the N-type work function adjustment layer.
A gate stack structure for a MOS varactor, comprising:
- a substrate including a channel region;
- a high-k dielectric layer on the channel region of the substrate;
- a P-type work function adjustment layer on the high-k dielectric layer;
- an N-type work function adjustment layer on the P-type work function adjustment layer;
- and
- a metal gate on the N-type work function adjustment layer,
- wherein the P-type work function adjustment layer comprises:
- a first portion and a second portion laterally adjacent to each other, the first portion being configured to adjust the work function of a PMOS device, and the second portion being configured to adjust the work function of an NMOS device.
A method for manufacturing a gate stack structure for a MOS varactor, the method comprising:
- providing a substrate including a channel region;
- forming a high-k dielectric layer on the channel region;
- forming a P-type work function layer on the high-k dielectric layer, the P-type work function adjustment layer including a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion;
- forming an N-type work function adjustment layer on the P-type work function adjustment layer;
- and
- forming a metal gate on the N-type work function adjustment layer.
Dependencies are inferred from the claim text.