Power Semiconductor Device Having Fully Depleted Channel Region

A power semiconductor device, comprising:

• a semiconductor body coupled to a first load terminal structure and a second load terminal structure and configured to conduct a load current;
• a first cell and a second cell, each being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
• a first mesa included in the first cell, the first mesa including a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region;
• a second mesa included in the second cell, the second mesa including a second port region having a second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region;
• each of the first mesa and the second mesa being spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and having a total extension of less than 100 nm in the direction, wherein the insulation structure houses;
• a control electrode structure for controlling the load current within the first mesa and the second mesa, the control electrode structure being electrically insulated from the first load terminal structure;
• and
• a guidance electrode electrically insulated from the control electrode structure and arranged in between the first mesa and the second mesa.