Power Semiconductor Device Having Fully Depleted Channel Regions

A power semiconductor device, comprising:

• a semiconductor body coupled to a first load terminal structure and a second load terminal structure:
• an active cell field implemented in the semiconductor body and configured to conduct a load current;
• a plurality of first cells and a plurality of second cells provided in the active cell field, each being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
• wherein:
• each first cell comprises a first mesa, the first mesa including:
• a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region;
• each second cell comprises a second mesa, the second mesa including:
• a second port region having the second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region;
• each first mesa and each second mesa are spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and having a total extension of less than 100 nm in said direction;
• wherein for at least 50% of the total area of the active cell field, a distance between one of the first cells and one of the second cells amounts to a pitch width, and a distance between two arbitrary first cells is at least three times the pitch width.

A power semiconductor device, comprising:

• a semiconductor body coupled to a first load terminal structure and a second load terminal structure:
• an active cell field implemented in the semiconductor body and configured to conduct a load current;
• a plurality of first cells and a plurality of second cells provided in the active cell field, each being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
• wherein:
• each first cell comprises a first mesa, the first mesa including:
• a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region;
• each second cell comprises a second mesa, the second mesa including:
• a second port region having the second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region;
• each first mesa and each second mesa are spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and having a total extension of less than 100 nm in said direction;
• wherein, for at least 50% of the total area of the active cell field, along the distance between two arbitrary first cells, there are provided at least two further cells, each further cell being either one of the second cells or a dummy cell.