Structure and method for memory cell array

An electronic device comprising a memory cell array structure, the memory cell array structure comprising:

• a semiconductor substrate;
• a plurality of memory cells arranged in m rows and n columns on the semiconductor substrate, m and n being positive integers, each of the memory cells including a first diode, a second diode, and a random access memory component;
• n columns of first well regions and n columns of second well regions spaced apart from each other in the semiconductor substrate and alternatively disposed along a column direction, the first well regions having a first conductivity type, and the second well regions having a second conductivity type different from the first conductivity type;
• m rows of first doped regions in the first well regions and having the second conductivity type, each one of first doped regions disposed in one of the first well regions along the column direction, one of the first doped regions and one of the first well regions disposed underneath thereof forming a first diode;
• m rows of second doped regions in the second well regions and having the first conductivity type, each one of second doped regions disposed in one of the second well regions along the column direction, one of the second doped regions and one of the second well regions disposed underneath thereof forming a second diode;
• a plurality of third doping regions having the first conductivity type of the first well regions, at least one of the third doped regions disposed in one of the first well regions, and the third doped regions being isolated from adjacent first doped regions;
• a plurality of fourth doping regions having the second conductivity type of the second well regions, at least one of the fourth doped regions disposed in one of the second well regions, and the fourth doped regions being isolated from adjacent second doped regions;
• a plurality of random access memory components disposed on the semiconductor substrate, each of the random access memory components having a bottom electrically connected to one of the first doped regions and one of the second doped regions;
• m rows of word lines on the random access memory components, spaced apart from each other and parallel to each other, each of the random access memory components having a top electrically connected to a same word line;
• n columns of reset lines each on third doped region in a same column and electrically connected to the third doped regions in the same column and underneath thereof, the rest lines being isolated from each other;
• n columns of bit lines each on fourth doped regions in a same column and electrically connected to the fourth doped regions in the same column and underneath thereof, the bit lines being isolated from each other.