Semiconductor memory device and method for fabricating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHARRY-HAK-LAY CHUANG, SHENG-HAUNG HAUNG, SHIH-CHANG LIU, CHERN-YOW HSU
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Abstract
A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.
Claims20
A method for fabricating a semiconductor memory device, the method comprising:
- exposing an electrode of a memory cell;
- forming a first capping layer on the electrode;
- etching a portion of the first capping layer to form a first trench reaching the electrode;
- and
- forming a first metal line in the first trench to contact the electrode.
A method for fabricating a semiconductor memory device, the method comprising:
- etching a first region of the semiconductor memory device to expose a first capping layer;
- forming a second capping layer on the first capping layer;
- etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line;
- and
- forming a second metal line in the first trench to contact the first metal line.
-20. (canceled)
A method of fabricating a semiconductor device, comprising:
- providing a first metal layer having a first line in a memory region and a second line in a logic region of a substrate;
- depositing a barrier layer over the first line and the second line;
- forming a first opening in the barrier layer in the memory region;
- forming a bottom electrode in the first opening and connected to the first line;
- disposing a magnetic tunnel junction (MTJ) structure on the bottom electrode;
- forming a top electrode on the MTJ structure;
- forming a capping layer on an exposed top surface of the top electrode in the memory region and over the logic region of the substrate;
- and
- performing an etching back process on the logic region removing the capping layer and exposing the barrier layer in the logic region.
Dependencies are inferred from the claim text.