Fin-type field-effect transistor
AssigneeInternational Business Machines Corporation
InventorKangguo Cheng
Life of this patent
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Abstract
This invention relates to a fin field-effect transistor semiconductor structure. The method of forming the semiconductor structure can include patterning a plurality of precursor fins on a semiconductor layer having a layer portion A and a layer portion B. The semiconductor layer can be located on a substrate. The layer portion B can be selectively etched to form B fins and a top half of precursor fins. The layer portion A can be selectively etched to form A fins and the substrate can be etched to form a bottom half of the decoupling fins. The precursor fins can be removed to expose the A fins, the decoupling fins, and the B fins. One of the A fins and the B fins can form n-type fins and the other can form p-type fins.
Claims20
A method of forming a semiconductor structure, the method comprising:
- patterning a plurality of precursor fins on a semiconductor layer comprising a layer portion A and a layer portion B;
- wherein the layer portion A and the layer portion B have one or both of a different strain level and a different chemical composition;
- and wherein the semiconductor layer is located on a substrate;
- selectively etching into the layer portion B to concurrently form a plurality of B fins and a top half of a plurality of decoupling fins;
- selectively etching into the layer portion A and the substrate to concurrently form a plurality of A fins and a bottom half of the plurality of decoupling fins;
- and
- removing the plurality of precursor fins to expose the plurality of A fins, the plurality of decoupling fins, and the plurality of B fins;
- wherein the plurality of A fins form a plurality of NFET fins and the plurality of B fins form a plurality of PFET fins;
- or wherein the plurality of A fins form the plurality of PFET fins and the plurality of B fins form the plurality of NFET fins.
A method of forming a semiconductor structure, the method comprising:
- patterning a plurality of precursor fins on a semiconductor layer comprising a layer portion A and a layer portion B;
- wherein the layer portion A and the layer portion B have one or both of a different strain level and a different chemical composition;
- and wherein a first portion of the precursor fins are located on the layer portion A and a second portion of the precursor fins are located on the layer portion B;
- and wherein the semiconductor layer is located on a substrate;
- masking the first portion of the precursor fins;
- after masking the first portion of the precursor fins, etching into the layer portion B to concurrently form a top half of a plurality of decoupling fins and a plurality of B fins;
- unmasking the first portion of the precursor fins;
- masking the plurality of B fins;
- after masking the plurality of B fins, etching into the layer portion A and the substrate to concurrently form a plurality of A fins and a bottom half of the plurality of decoupling fins;
- and
- unmasking the plurality of B fins;
- and
- removing the plurality of precursor fins to expose the plurality of A fins, the plurality of decoupling fins, and the plurality of B fins;
- wherein the plurality of A fins form a plurality of NFET fins and the plurality of B fins form a plurality of PFET fins;
- or wherein the plurality of A fins form the plurality of PFET fins and the plurality of B fins form the plurality of NFET fins.
A semiconductor structure, comprising:
- a substrate;
- a plurality of fins located on the substrate;
- wherein the plurality of fins comprises a plurality of NFET fins, a plurality of PFET fins, and a plurality of decoupling fins;
- wherein a height y of the plurality of decoupling fins is greater than one or both of a height x of the plurality of NFET fins and a height y of the plurality of PFET fins;
- and wherein the plurality of NFET fins has a width n and the plurality of PFET fins has a width p;
- and
- wherein one or both of the following conditions is satisfied:
- (ln−pl)/n*100≦10% and (ln−pl)/p *100≦10%.
Dependencies are inferred from the claim text.