Coplanar Type Oxide Thin Film Transistor, Method of Manufacturing the Same, and Display Panel and Display Device Using the Same

A display panel comprising:

• a plurality of gate lines that receive a plurality of gate pulses;
• a plurality of data lines that receive a plurality of data voltages;
• and
• a plurality of pixels defined by the plurality of gate lines and the plurality of data lines,
• wherein each of the plurality of pixels comprises an oxide thin film transistor (TFT) comprising:
• a light shielding layer;
• a buffer provided on the light shielding layer;
• a semiconductor layer provided on the buffer, the semiconductor layer including an oxide semiconductor material and comprising an active area, a first conductor adjacent to a first end of the active area, and a second conductor adjacent to a second end of the active area;
• a gate insulation layer covering the semiconductor layer and the buffer;
• a gate electrode provided on the gate insulation layer and overlapping a portion of the semiconductor layer;
• and
• a passivation layer covering the gate electrode and the gate insulation layer,
• wherein a resistance of the active area is different from a resistance of the first conductor and a resistance of the second conductor, and
• wherein a width of the active area is aligned with a width of the light shielding layer.

A method of manufacturing an oxide thin film transistor (TFT), the method comprising:

• forming a light shielding layer on a substrate;
• depositing a buffer on the substrate;
• forming a semiconductor layer including an oxide semiconductor material on the buffer;
• depositing a gate insulation layer that covers the semiconductor layer and the buffer;
• depositing a gate electrode overlapping the semiconductor layer;
• decreasing a resistance of a first area and a second area of the semiconductor layer, the first area at a first end of an active area of the semiconductor layer and the second area at a second end of the active area of the semiconductor layer, the first area with the decreased resistance forming a first conductor and the second area with the decreased resistance forming a second conductor while the gate insulation layer is covering the semiconductor layer and the buffer,
• wherein decreasing the resistance of the first area and the second area comprises irradiating ultraviolet (UV) light on the semiconductor layer, the UV light being irradiated from below the substrate.