Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsSatoshi NAGASHIMA, Tatsuya KATO
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Abstract
A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.
Claims13
A semiconductor memory device, comprising:
- a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction;
- two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction;
- and
- an electrode film disposed between each of the semiconductor pillars and each of the interconnects,
- the two interconnects being drivable independently from each other.
A semiconductor memory device, comprising:
- a plurality of first interconnects extending in a first direction and being arranged along a second direction crossing the first direction;
- a plurality of semiconductor pillars extending in a third direction, being arranged in one column along the first direction between the (4n+1)th (n being an integer of 0 or more) first interconnect and the (4n+2)th first interconnect and between the (4n+3)th first interconnect and the (4n+4)th first interconnect counting in the second direction, and not being disposed between the (4n+2)th first interconnect and the (4n+3)th first interconnect counting in the second direction, the third direction crossing the first direction and the second direction;
- and
- an electrode film between each of the semiconductor pillars and each of the first interconnects,
- the (4n+1)th first interconnect and the (4n+4)th first interconnect being connected to each other,
- the (4n+2)th first interconnect and the (4n+3)th first interconnect being connected to each other,
- a first interconnect group including the (4n+1)th first interconnect and the (4n+4)th first interconnect and a second interconnect group including the (4n+2)th first interconnect and the (4n+3)th first interconnect being drivable independently from each other.
Dependencies are inferred from the claim text.