Ferroelectric memory and methods of forming the same

A memory cell, comprising:

• a buried recessed access device (BRAD) formed in a substrate, wherein a gate of the BRAD is formed between a first source/drain region and a second source/drain region corresponding to the BRAD, and wherein the gate is formed below an upper surface of at least one of the first and the second source/drain region;
• a ferroelectric capacitor formed on the BRAD, wherein a bottom electrode of the ferroelectric capacitor is coupled to the first source/drain region, and wherein a top electrode of the ferroelectric capacitor is coupled to the second source/drain region;
• and
• a conductive contact coupled to the top electrode and to the second source/drain region, wherein the conductive contact is not positioned in alignment with the ferroelectric capacitor and an adjacent ferroelectric capacitor of an adjacent memory cell.

A ferroelectric random access memory (FeRAM), comprising:

• a first plurality of ferroelectric capacitors coupled in series between a first conductive line and a second conductive line;
• and
• a second plurality of ferroelectric capacitors coupled in series between the first conductive line and a third conductive line;
• wherein each of the first and second plurality of ferroelectric capacitors are coupled to a respective buried recessed access device (BRAD) having a gate electrode formed beneath the corresponding ferroelectric capacitor;
• wherein each of the first plurality of ferroelectric capacitors are formed in a container and include:
• a bottom electrode formed on sidewalls of the container and on a bottom electrode contact;
• a ferroelectric material formed in the container and on sidewalls of the bottom electrode;
• and
• a top electrode formed in the container and on sidewalls of the ferroelectric material, the top electrode coupled to a source/drain region of the corresponding BRAD via a conductive pillar, wherein a distance from the conductive pillar to a first side of a ferroelectric capacitor of the first plurality is different than a distance from the conductive pillar to a second side of the ferroelectric capacitor of the first plurality.

A method for forming a ferroelectric random access memory (FeRAM), comprising:

• forming a first plurality of buried recessed access devices (BRAD) corresponding to a respective first plurality of memory cells;
• forming a first plurality of ferroelectric capacitors on the first plurality of BRADs;
• and
• forming a second plurality of BRADs corresponding to a respective second plurality of memory cells;
• and
• forming a second plurality of ferroelectric capacitors on the second plurality of BRADs;
• wherein the first plurality of ferroelectric capacitors are coupled in series with each other between a first conductive line and a second conductive line;
• and
• wherein the second plurality of ferroelectric capacitors are coupled in series with each other between the first conductive line and a third conductive line;
• and
• forming an isolation region between the first plurality of BRADs and the second plurality of BRADs;
• and
• forming at least a portion of a conductive pillar on a dielectric material corresponding to the isolation region.