Semiconductor device, static random access memory cell and manufacturing method of semiconductor device

A static random access memory (SRAM) cell comprising:

• a substrate;
• a first semiconductor fin over the substrate and electrically coupled as a source/drain of a first pull-down (PD) transistor and a source/drain of a first pass-gate (PG) transistor;
• a second semiconductor fin over the substrate and electrically coupled as a source/drain of a first pull-up (PU) transistor;
• a third semiconductor fin over the substrate and electrically coupled as a source/drain of a second PD transistor and a source/drain of a second PG transistor;
• a fourth semiconductor fin over the substrate and electrically coupled as a source/drain of a second PU transistor;
• at least one epitaxy structure over at least one of the first semiconductor fin, the second semiconductor fin, the third semiconductor fin, and the fourth semiconductor fin;
• and
• a plurality of dielectric fin sidewall structures on opposite sides of the epitaxy structure.

A method for manufacturing a static random access memory (SRAM) cell comprising:

• forming two pull-up (PU) transistors, two pass-gate (PG) transistors, and two pull-down (PD) transistors electrically connected to form the SRAM cell, wherein the forming at least one of the PU transistors, the PG transistors, and the PD transistors comprises:
• forming a semiconductor fin;
• forming a plurality of dielectric fin sidewall structures on opposite sides of the semiconductor fin;
• recessing a portion of the semiconductor fin between the dielectric fin sidewall structures;
• and
• forming an epitaxy structure on the recessed portion of the semiconductor fin.