Circuit design system and semiconductor circuit designed by using the system
AssigneeSamsung Electronics Co., Ltd.
InventorsKyong-Taek Lee, Sang-Woo Pae, Hye-Jin Kim, June-Kyun Park, Hyun-Woo Lee
Life of this patent
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Abstract
A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.
Claims20
A circuit design system comprising:
- a processor;
- a storage in which a plurality of transistor designs are stored;
- and
- a design module designing a circuit based on the plurality of transistor designs according to defined requirements by the processor,
- wherein the plurality of transistor designs are designs for transistors each including a gate insulating film with a high-k dielectric layer, wherein the design module analyzes a circuit design, selects a first transistor design whereby the first transistor design operates within the circuit in a region where a drain voltage is higher than a gate voltage, and substitutes a second transistor design having a smaller size than the first transistor design for the selected first transistor design, wherein a second drain-gate voltage of the second transistor design operating in an accumulation mode is higher than a first drain-gate voltage of the first transistor design operating in the accumulation mode.
A circuit design method comprising:
- analyzing a semiconductor circuit design including a plurality of transistors and selecting a first NMOS transistor design from among the plurality of transistors within the circuit design, the first NMOS transistor operating in a region where a drain voltage is higher than a gate voltage;
- and
- substituting a second NMOS transistor having a smaller size than the first NMOS transistor for the first NMOS transistor in the semiconductor circuit,
- wherein the first NMOS transistor includes a gate insulating film without a high-k dielectric layer and the second NMOS transistor includes a gate insulating film with a high-k dielectric layer, and a second drain-gate voltage of the second NMOS transistor operating in an accumulation mode is higher than a first drain-gate voltage of the first NMOS transistor operating in the accumulation mode.
A computer-readable recording medium including a program for executing a circuit design method, the circuit design method circuit design method comprising:
- analyzing a semiconductor circuit including a plurality of transistors and selecting a first NMOS transistor from among the plurality of transistors, the first NMOS transistor operating in a region where a drain voltage is higher than a gate voltage;
- and
- substituting a second NMOS transistor having a smaller size than the first NMOS transistor for the first NMOS transistor,
- wherein the first NMOS transistor includes a gate insulating film without a high-k dielectric layer and the second NMOS transistor includes a gate insulating film with a high-k dielectric layer, and a second drain-gate voltage of the second NMOS transistor operating in an accumulation mode is higher than a first drain-gate voltage of the first NMOS transistor operating in the accumulation mode.
A circuit design method comprising:
- analyzing a semiconductor circuit design including a plurality of MOS transistors and selecting a first transistor that operates within the circuit with its drain voltage higher than its gate voltage;
- and
- substituting in the circuit design a second, smaller transistor having a gate insulating film with a high-k dielectric layer, for the first transistor.
Dependencies are inferred from the claim text.