Integrated metal gate cmos devices
AssigneeInternational Business Machines Corporation
InventorsRuqiang Bao, Dechao Guo, Vijay Narayanan
Life of this patent
Estimating the term…
Abstract
A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
Claims20
A semiconductor device comprising:
- a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region;
- a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region;
- a first gate stack arranged on the first channel region, the first gate stack comprising:
- a first metal layer arranged on the first channel region;
- a work function metal layer arranged on the first metal layer;
- and
- another work function metal arranged on the work function metal layer;
- and
- a second gate stack arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
A semiconductor device comprising:
- a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region;
- a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region;
- a first gate stack arranged on the first channel region, the first gate stack comprising:
- a barrier metal layer arranged on the first channel region;
- a first metal layer arranged on the barrier metal layer;
- a work function metal layer arranged on the first metal layer;
- and
- another work function metal arranged on the work function metal layer;
- and
- a second gate stack arranged on the second channel region, the second gate stack comprising:
- a first metal layer arranged on the second channel region;
- a sacrificial patterning layer arranged on the first metal layer;
- a work function metal layer arranged on the second nitride layer;
- and
- another work function metal arranged on the work function metal layer.
Dependencies are inferred from the claim text.