Power Semiconductor Device Having Fully Depleted Channel Regions
AssigneeInfineon Technologies AG
InventorsAnton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
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AssigneeInfineon Technologies AG
InventorsAnton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
Estimating the term…
A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.
A power semiconductor device, comprising:
A method of operating a power semiconductor device that includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure and configured to conduct a load current, a first cell and a second cell, each being configured for controlling the load current and each being electrically connected to the first load terminal structure on the one side and electrically connected to a drift region of the semiconductor body on the other side, the drift region having a first conductivity type, a first mesa included in the first cell, the first mesa including:
Dependencies are inferred from the claim text.