Vertical transistors and methods of forming same
AssigneeGlobalfoundries Inc.
InventorsBrent A. Anderson, Edward J. Nowak
Life of this patent
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Abstract
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within a dielectric layer and over the central region of the fin; a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source drain region, wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.
Claims27
A method of forming a vertical transistor, the method comprising:
- forming a first dielectric layer over a substrate and adjacent to a fin that is disposed over the substrate;
- oxidizing sidewalls of the fin to form an oxidized portion of the fin at the sidewalls at a central region of the fin;
- removing the oxidized portion of the fin from the sidewalls at the central region of the fin, thereby forming at least one tapered region of the fin, wherein the at least one tapered region of the fin is formed above the central region or below the central region;
- forming a gate structure over the first dielectric layer and around at least a portion of the central region of the fin;
- removing the first dielectric layer to form voids directly adjacent to the fin in an area over the substrate and beneath the gate structure;
- growing a first epitaxial layer within the voids such that the first epitaxial layer is disposed substantially around the fin in the area over the substrate and beneath the gate structure;
- performing a first anneal to form a first source/drain region within the fin;
- growing a second epitaxial layer over a top surface of the fin;
- and
- performing a second anneal to form a second source/drain region within the fin, thereby creating the vertical transistor.
A method of forming a vertical transistor, the method comprising:
- forming a pair of fins over a substrate, wherein each fin in the pair of fins includes a tapered sidewall on a side of the fin that faces another fin in the pair of fins;
- forming a first dielectric layer over the substrate and adjacent to each fin;
- forming a gate structure over the first dielectric layer and around each fin of the pair of fins;
- removing the first dielectric layer such that voids are created adjacent to each fin in an area over the substrate and beneath the gate structure;
- growing a first epitaxial layer within the voids such that the first epitaxial layer is disposed substantially around each fin in the area over the substrate and beneath the gate structure;
- performing a first anneal to form a first source/drain region within each fin;
- growing a second epitaxial layer over a top surface of each fin;
- and
- performing a second anneal to form a second source/drain region within each fin, thereby creating the vertical transistor.
A vertical transistor comprising:
- a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within an inter-level dielectric (ILD) layer and over the central region of the fin;
- and
- a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source/drain region,
- wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.
A vertical transistor comprising:
- a pair of fins over a substrate;
- a gate structure within an inter-level dielectric (ILD) layer substantially surrounding each fin in the pair of fins;
- a first source/drain region within each fin below the gate structure;
- a second source/drain region with each fin over the gate structure,
- wherein each fin in the pair of fins includes a tapered sidewall on a side of the fin that faces the another fin in the pair of fins.
Dependencies are inferred from the claim text.