Circuitry with voltage limiting and capactive enhancement

An apparatus comprising:

• a cascode circuit susceptible to overvoltage conditions including avalanche breakdown, the cascode circuit including:
• a first transistor having a gate, a source, a channel and a drain;
• and
• a second transistor having a gate, a source, a channel and a drain electrically connected to the source of the first transistor, the second transistor being configured and arranged to control the first transistor in an off state by applying a voltage to the gate of the first transistor;
• a plurality of conductive trenches;
• and
• a set of one or more doped regions, each doped region being between a respective adjacent pair of the conductive trenches and configured to provide a p-n junction, wherein the plurality of conductive trenches and one or more doped regions are configured and arranged with the cascode circuit to provide capacitance across the source and the drain of the second transistor and to mitigate avalanche breakdown of the second transistor by restricting a voltage level at the source or the drain of the second transistor,
• wherein the one or more doped regions and the conductive trenches are part of a circuit connected to the source and drain of the second transistor in parallel with the channel of the second transistor, and the conductive trenches are arranged laterally adjacent one another with the one or more doped regions laterally between the conductive trenches.