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US 2018/0006013 A1Published application
Contact array optimization for esd devices
AssigneeTexas Instruments Incorporated
InventorsHe LIN, Kun CHEN, Chao WU, Dening WANG, Lily SPRINGER, Andy STRACHAN, Gang XUE
Life of this patent
Estimating the term…
Abstract
A contact array optimization scheme for ESD devices. In one embodiment, contact apertures patterned through a pre-metal dielectric layer over active areas may be selectively modified in size, shape, placement and the like, to increase ESD protection performance, e.g., such as maximizing the transient current density, etc., in a standard ESD rating test.
Claims22
A semiconductor fabrication method, comprising:
- forming an active area as part of an electrostatic discharge (ESD) protection circuit in a semiconductor substrate according to a select process technology;
- forming a dielectric layer over the active area;
- patterning the dielectric layer to define contact apertures overlapping the active area, the contact apertures each having a size based on an ESD protection parameter of the ESD protection circuit;
- and
- depositing a metallic composition to fill the contact apertures to provide an electrical conductive path between the active area and a metal layer deposited over the dielectric layer,
- wherein the contact apertures are defined as an array using a contact layer mask having an aperture size for a subset of contact apertures of a peripheral annulus region of the array larger than a size specified in the select process technology but complying with critical dimension (CD) rules and design rule checking (DRC) associated with the select process technology.
3 more elements
-11. (canceled)
An integrated circuit, comprising:
- an active area formed as part of an electrostatic discharge (ESD) protection circuit in a semiconductor substrate according to a select process technology;
- a dielectric layer over the active area;
- a metal layer disposed on the dielectric layer;
- and
- a contact structure formed between the active area and the metal layer, the contact structure having contact apertures patterned through the dielectric layer and filled with a metallic composition to provide an electrical conductive path between the active area and the metal layer, the contact apertures each having a size based on an ESD protection parameter of the ESD protection circuit,
- wherein the contact apertures are defined as an array using a contact layer mask having an aperture size for a subset of contact apertures of a peripheral annulus region of the array larger than a size specified in the select process technology but complying with critical dimension (CD) rules and design rule checking (DRC) associated with the select process technology.
3 more elements
-23. (canceled)
A semiconductor fabrication method, comprising:
- forming an active area as part of an electrostatic discharge (ESD) protection circuit in a semiconductor substrate according to a select process technology;
- forming a dielectric layer over the active area;
- patterning the dielectric layer to define contact apertures overlapping the active area, the contact apertures each having a size based on an ESD protection parameter of the ESD protection circuit;
- and
- depositing a metallic composition to fill the contact apertures to provide an electrical conductive path between the active area and a metal layer deposited over the dielectric layer,
- wherein the contact apertures are defined as an array using a contact layer mask, each contact aperture having a rectangular shape and arranged in a staggered array.
3 more elements
A semiconductor fabrication method, comprising:
- forming an active area as part of an electrostatic discharge (ESD) protection circuit in a semiconductor substrate according to a select process technology;
- forming a dielectric layer over the active area;
- patterning the dielectric layer to define contact apertures overlapping the active area, the contact apertures each having a size based on an ESD protection parameter of the ESD protection circuit;
- and
- depositing a metallic composition to fill the contact apertures to provide an electrical conductive path between the active area and a metal layer deposited over the dielectric layer,
- wherein the contact apertures are defined as an array using a contact layer mask, the array having at least a corner devoid of any contact aperture, each contact aperture having an aperture size larger than a size specified in the select process technology but complying with critical dimension (CD) rules and design rule checking (DRC) associated with the select process technology, and
- wherein the array of contact apertures is surrounded by a continuous trench contact aperture positioned along a periphery of the array.
4 more elements
A semiconductor fabrication method, comprising:
- forming an active area as part of an electrostatic discharge (ESD) protection circuit in a semiconductor substrate according to a select process technology;
- forming a dielectric layer over the active area;
- patterning the dielectric layer to define contact apertures overlapping the active area, the contact apertures each having a size based on an ESD protection parameter of the ESD protection circuit;
- and
- depositing a metallic composition to fill the contact apertures to provide an electrical conductive path between the active area and a metal layer deposited over the dielectric layer,
- wherein the contact apertures are defined as continuous trench contact apertures arranged as a plurality of concentric circles.
3 more elements
A semiconductor fabrication method, comprising:
- forming an active area as part of an electrostatic discharge (ESD) protection circuit in a semiconductor substrate according to a select process technology;
- forming a dielectric layer over the active area;
- patterning the dielectric layer to define contact apertures overlapping the active area, the contact apertures each having a size based on an ESD protection parameter of the ESD protection circuit;
- and
- depositing a metallic composition to fill the contact apertures to provide an electrical conductive path between the active area and a metal layer deposited over the dielectric layer,
- wherein the contact apertures are defined as continuous trench contact apertures arranged in a plurality of concentric race tracks.
3 more elements
An integrated circuit, comprising:
- an active area formed as part of an electrostatic discharge (ESD) protection circuit in a semiconductor substrate according to a select process technology;
- a dielectric layer over the active area;
- a metal layer disposed on the dielectric layer;
- and
- a contact structure formed between the active area and the metal layer, the contact structure having contact apertures patterned through the dielectric layer and filled with a metallic composition to provide an electrical conductive path between the active area and the metal layer, the contact apertures each having a size based on an ESD protection parameter of the ESD protection circuit,
- wherein the contact apertures are defined as an array using a contact layer mask, each contact aperture having a rectangular shape and arranged in a staggered array.
3 more elements
An integrated circuit, comprising:
- an active area formed as part of an electrostatic discharge (ESD) protection circuit in a semiconductor substrate according to a select process technology;
- a dielectric layer over the active area;
- a metal layer disposed on the dielectric layer;
- and
- a contact structure formed between the active area and the metal layer, the contact structure having contact apertures patterned through the dielectric layer and filled with a metallic composition to provide an electrical conductive path between the active area and the metal layer, the contact apertures each having a size based on an ESD protection parameter of the ESD protection circuit,
- wherein the contact apertures are defined as an array using a contact layer mask, the array having at least a corner devoid of any contact aperture, each contact aperture having an aperture size larger than a size specified in the select process technology but complying with critical dimension (CD) rules and design rule checking (DRC) associated with the select process technology,
- wherein the array of contact apertures is surrounded by a continuous trench contact aperture positioned along a periphery of the array.
4 more elements
An integrated circuit, comprising:
- an active area formed as part of an electrostatic discharge (ESD) protection circuit in a semiconductor substrate according to a select process technology;
- a dielectric layer over the active area;
- a metal layer disposed on the dielectric layer;
- and
- a contact structure formed between the active area and the metal layer, the contact structure having contact apertures patterned through the dielectric layer and filled with a metallic composition to provide an electrical conductive path between the active area and the metal layer, the contact apertures each having a size based on an ESD protection parameter of the ESD protection circuit,
- wherein the contact apertures are defined as continuous trench contact apertures arranged in a plurality of concentric circles.
3 more elements
An integrated circuit, comprising:
- an active area formed as part of an electrostatic discharge (ESD) protection circuit in a semiconductor substrate according to a select process technology;
- a dielectric layer over the active area;
- a metal layer disposed on the dielectric layer;
- and
- a contact structure formed between the active area and the metal layer, the contact structure having contact apertures patterned through the dielectric layer and filled with a metallic composition to provide an electrical conductive path between the active area and the metal layer, the contact apertures each having a size based on an ESD protection parameter of the ESD protection circuit,
- wherein the contact apertures are defined as continuous trench contact apertures arranged in a plurality of concentric race tracks.
3 more elements
Dependencies are inferred from the claim text.