Semiconductor package and method of manufacturing the same

A method comprising:

• providing a first sub-package unit including at least two first semiconductor chips, which are vertically stacked, and a first mold layer surrounding side surfaces of the at least two first semiconductor chips;
• and
• providing a second sub-package unit including at least two second semiconductor chips, which are vertically stacked, and a second mold layer that surrounds side surfaces of the at least two second semiconductor chips and is vertically spaced apart from the first mold layer, the second sub-package unit being disposed on the first sub-package unit,
• wherein the at least two first semiconductor chips and the at least two second semiconductor chips each include a through substrate via (TSV), and
• wherein a top-most semiconductor chip of the at least two first semiconductor chips is electrically connected to the bottom-most semiconductor chip of the at least two second semiconductor chips, without a package substrate therebetween;
• and
• providing a package substrate on which the at least two first semiconductor chips and the at least two second semiconductor chips are vertically stacked to form a semiconductor package.