Semiconductor chip package and fabrication method thereof

A semiconductor chip package, comprising:

• a substrate;
• a semiconductor die mounted on the substrate, wherein the semiconductor die comprises a bond pad disposed on an active surface of the semiconductor die, and a passivation layer covering perimeter of the bond pad, wherein a bond pad opening in the passivation layer exposes a central area of the bond pad;
• a conductive paste post printed on the exposed central area of the bond pad;
• a conductive trace printed on the passivation layer and being electrically connected to the conductive paste post;
• a redistributed bond pad printed on the passivation layer, wherein the redistributed bond pad is electrically connected to the conductive paste post through the conductive trace;
• and
• a bonding wire secured to a top surface of the redistributed bond pad.

A package-on-package, comprising:

• a bottom package comprising a first semiconductor die mounted on a substrate, and a plurality of solder balls mounted on a lower surface of the substrate, wherein the first semiconductor die is encapsulated by a first molding compound;
• conductive traces printed on the first molding compound;
• and
• a second semiconductor die mounted on the first molding compound.