Layout of transmission vias for memory device
AssigneeMicron Technology, Inc.
InventorKayoko Shibata
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory cell arrays arranged in line in a first direction in the substrate; a first set of through electrodes arranged between the first and second memory cell arrays, each of the first set of through electrodes penetrating through the substrate, the first set of through electrodes including first and second through electrodes; and a second set of through electrodes arranged between the second and third memory cell arrays, each of the second set of through electrodes penetrating through the substrate, the second set of through electrodes including third and fourth through electrodes.
Claims18
An apparatus comprising:
- a chip extending on a plane defined by a first direction and a second direction perpendicular to the first direction, the chip comprising:
- a substrate;
- first, second and third memory cell arrays arranged in the first direction in the substrate;
- a plurality of first through electrodes arranged in line in the second direction between the first and second memory cell arrays;
- and
- a plurality of second through electrodes arranged in line in the second direction between the second and third memory cell arrays.
An apparatus comprising:
- an interposer including a plurality of terminals, and
- a first chip stacked on the interposer, the first chip including:
- a first substrate;
- a plurality of first through electrodes in the first substrate, the plurality of first through electrodes are physically coupled to the interposer via the plurality of terminals;
- and
- a plurality of second through electrodes in the first substrate, the plurality of second through electrodes are physically decoupled to the interposer;
- and
- a second chip stacked on the first chip, the second chip including:
- a second substrate;
- first, second and third memory cell arrays arranged in line in the second substrate;
- a plurality of third through electrodes between the first and second memory cell arrays in the second substrate, each of the plurality of third through electrodes being coupled to and provided directly above a corresponding one of the plurality of second through electrodes;
- and
- a plurality of fourth through electrodes between the second and third memory cell arrays in the second substrate, each of the plurality of fourth through electrodes being coupled to and provided directly above a corresponding one of the plurality of first through electrodes.
Dependencies are inferred from the claim text.