Package and packaging process of a semiconductor device
AssigneeWinbond Electronics Corp.
InventorYu-Ming Chen
Life of this patent
Estimating the term…
Abstract
A packaging process of a semiconductor device includes following steps. A patterned conductive layer and a solder resist layer that covers the patterned conductive layer are formed through 3D-printing over a carrier having a cavity. The patterned conductive layer and the solder resist layer extend to the outside of the cavity from the inside of the cavity. One portion of the patterned conductive layer is exposed by the solder resist layer. At least one semiconductor device is mounted on the patterned conductive layer in the cavity, such that the at least one semiconductor device is electrically connected to the patterned conductive layer.
Claims16
A packaging process of a semiconductor device, comprising:
- forming a patterned conductive layer and a solder resist layer through three-dimensional printing over a carrier having a cavity, wherein the solder resist layer covers the patterned conductive layer, the patterned conductive layer and the solder resist layer extend to an outside of the cavity from an inside of the cavity, and one portion of the patterned conductive layer is exposed by the solder resist layer;
- mounting at least one semiconductor device on the patterned conductive layer in the cavity, such that the at least one semiconductor device is electrically connected to the patterned conductive layer;
- forming at least one tapered extension structure in the cavity, wherein the at least one tapered extension structure has a inclined layout surface, and the inclined layout surface of the at least one tapered extension structure extends from an active surface of the first semiconductor device to a bottom surface of the cavity;
- and
- forming a plurality of connecting traces on the active surface, the inclined layout surface, and the bottom surface through three-dimensional printing, wherein the connecting traces are electrically connected between the semiconductor device and the patterned conductive layer in the cavity.
(canceled)
A semiconductor device package comprising:
- a carrier having a cavity;
- a patterned conductive layer;
- a solder resist layer covering the patterned conductive layer, wherein the patterned conductive layer and the solder resist layer extend from an inside of the cavity to an outside of the cavity, and one portion of the patterned conductive layer is exposed by the solder resist layer;
- a first semiconductor device mounted on the patterned conductive layer in the cavity, wherein the first semiconductor device has a first back surface facing the carrier and a first active surface opposite to the first back surface;
- a first tapered extension structure disposed on a bottom surface of the cavity, the first tapered extension structure having a first inclined layout surface extending from the first active surface to the bottom surface;
- and
- a plurality of connecting traces on the first active surface, the first inclined layout surface, and the bottom surface, such that the connecting traces are electrically connected between the first semiconductor device and the patterned conductive layer in the cavity.
Dependencies are inferred from the claim text.