Package-on-package semiconductor device assemblies including one or more windows and related methods and packages

An assembly of semiconductor device packages, comprising:

• a first semiconductor device package, comprising:
• a first substrate comprising a first array of electrically conductive elements located on an upper surface of the first substrate;
• a first semiconductor device on the upper surface of the first substrate;
• and
• a heat-management structure supported on an upper surface of the first semiconductor device;
• and
• a second semiconductor device package supported on the first semiconductor device package, comprising:
• a second substrate comprising a second array of electrically conductive elements located on a lower surface of the second substrate;
• a window extending through the second substrate from the lower surface to an upper surface of the second substrate, the second array of electrically conductive elements at least partially laterally surrounding a periphery of the window, the second substrate extending laterally beyond the second array of electrically conductive elements;
• and
• additional semiconductor devices supported on the upper surface of the second substrate around a periphery of the array of electrically conductive elements, the additional semiconductor devices being electrically connected to at least some of the electrically conductive elements of the second array by routing elements extending from the additional semiconductor devices toward the window;
• wherein at least a portion of the heat-management structure is located within the window, and wherein at least a portion of an outer periphery of the first substrate is coupled to an inner portion of the second substrate defining the periphery of the window.

A method of making a semiconductor device assembly, comprising:

• positioning a processing unit supported on an upper surface of a first substrate at least partially through a window in a second substrate overlying the first substrate;
• positioning a heat-management structure supported on an upper surface of the processing unit at least partially through the window;
• and
• electrically connecting at least some electrically conductive elements of a first array of electrically conductive elements located on the upper surface of the first substrate with at least some corresponding electrically conductive elements of a second array of electrically conductive elements located on a lower surface of the second substrate.