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US 2018/0005980 A1Published application
Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops
AssigneeKulicke and Soffa Industries, Inc.
InventorsBasil Milton, Wei Qin
Life of this patent
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Abstract
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
Claims23
A method of generating a wire loop profile in connection with a semiconductor package, the method comprising the steps of:
- (a) providing package data related to the semiconductor package;
- and
- (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
Dependencies are inferred from the claim text.