Rlink - on-die inductor structures to improve signaling

An electronic system comprising:

• a first integrated circuit chip having:
• a data signal transmitter circuit disposed on a horizontal inner layer within the first chip and having a data signal output contact of the first chip;
• a data signal surface contact disposed on a horizontal surface of the first chip;
• a first data signal inductor of the first chip having (1) a second end electrically coupled to a capacitance value of an electrostatic discharge (ESD) circuit of the first chip, and (2) a first end electrically coupled to a capacitance value at the data signal surface contact and to the data signal surface contact of the first chip;
• and
• a second data signal inductor of the first chip having (1) a second end electrically coupled to the data signal output contact of the data signal circuit of the first chip, and to a capacitance value of the data signal circuit of the first chip, (2) a first end electrically coupled to a second end of the first data signal inductor of the first chip, and to the capacitance value of the ESD circuit of the first chip, wherein loops of the first data signal inductor are disposed within a last silicon metal level LSML and a LSML-1 level of the first chip, and wherein loops of the second data signal inductor are disposed within the LSML-1 level of the first chip;
• a second integrated circuit chip having:
• a data signal receiver circuit disposed on a horizontal inner layer within the second chip and having a data signal output contact of the second chip;
• a data signal surface contact disposed on a horizontal surface of the second chip and electrically coupled to the data signal output contact of the second chip;
• and
• a chip package electrically coupling the data signal surface contact of the first chip to the data signal surface contact of the second chip.

An electronic system comprising:

• a first integrated circuit chip having:
• a data signal transmitter circuit disposed on a horizontal inner layer within the first chip and having a data signal output contact of the first chip;
• a data signal surface contact disposed on a horizontal surface of the first chip;
• a first data signal inductor of the first chip having (1) a second end electrically coupled to a capacitance value of an electrostatic discharge (ESD) circuit of the first chip, and (2) a first end electrically coupled to a capacitance value at the data signal surface contact and to the data signal surface contact of the first chip;
• and
• a second data signal inductor of the first chip having (1) a second end electrically coupled to the data signal output contact of the data signal circuit of the first chip, and to a capacitance value of the data signal circuit of the first chip, (2) a first end electrically coupled to a second end of the first data signal inductor of the first chip, and to the capacitance value of the ESD circuit of the first chip;
• a second integrated circuit chip having:
• a data signal receiver circuit disposed on a horizontal inner layer within the second chip and having a data signal output contact of the second chip;
• a data signal surface contact disposed on a horizontal surface of the second chip and electrically coupled to the data signal output contact of the second chip;
• a first data signal inductor of the second chip having (1) a second end electrically coupled to a capacitance value of an electrostatic discharge (ESD) circuit of the second chip, and (2) a first end electrically coupled to a capacitance value at the data signal surface contact and to the data signal surface contact of the second chip;
• a second data signal inductor of the second chip having (1) a second end electrically coupled to the data signal output contact of the data signal circuit of the second chip, and to a capacitance value of the data signal circuit of the second chip, (2) a first end electrically coupled to a second end of the first data signal inductor of the second chip, and to the capacitance value of the ESD circuit of the second chip;
• wherein loops of the first data signal inductor of the first and second chips cross on different levels of the chip of the first and second chips with loops of the second data signal inductor of the first and second chips so that a data signal transmitted by the data signal transmit circuit flow in the same direction through the loops of the first and second data signal inductors of the first and second chips;
• and
• a chip package electrically coupling the data signal surface contact of the first chip to the data signal surface contact of the second chip.