# US 2018/0005962 A1 · Damaging integrated circuit components > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0005962 A1 - Document ID: US20180005962A1 - Status: Published application - Kind: A1 - Application number: 15/198,709 - Filed: 2016-06-30 - Published: 2018-01-04 - Earliest claimed: 2016-06-30 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Cyril Cabral, JR.; Kenneth P. Rodbell - Web page: https://patentgrep.com/patent/US20180005962A1 ## CPC - H10W 42/40: protecting against tampering, e.g. unauthorised inspection or reverse engineering - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10W 20/067: {by modifying the pattern of conductive parts} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The FEOL portion rests on top of and in contact with the substrate. The integrated circuit structure includes a memory level portion. The memory level portion rests on top of and in contact with the FEOL portion. The integrated circuit structure includes a back-end-of-the-line (BEOL) portion. The BEOL portion rests on top of and in contact with the memory level portion. The integrated circuit structure includes a multiple layer that includes one or more pairs of reactive materials. The multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate. ## Claims ### Claim 1 A method comprising: forming a multiple layer within an integrated circuit region, wherein the multiple layer includes one or more pairs of reactive materials; igniting the multiple layer so that the one or more pairs of reactive materials react pairwise in one or more exothermic reactions; and damaging one or more components of an integrated circuit with energy released by the one or more exothermic reactions such that the one or more components are rendered, at least in part, permanently inoperable. ### Claim 2 (depends on 1) The method of claim 1, wherein within the integrated circuit region is one or more of: i) on top of a back-end-of-the-line (BEOL) portion; ii) within the BEOL portion; iii) within a memory level portion; iv) within a front-end-of-the-line (FEOL) portion; v) embedded in a substrate; and vi) on bottom of a thinned substrate. ### Claim 3 (depends on 1) The method of claim 1, wherein the one or more components of the integrated circuit that are damaged are one or more of: i) one or more interconnects; ii) one or more transistors; iii) one or more memory arrays; and iv) circuitry for one or more applications. ### Claim 4 (depends on 1) The method of claim 1, wherein the one or more pairs of reactive materials are selected from the group consisting of: aluminum (Al), antimony (Sb), barium (Ba), beryllium (Be), bismuth (Bi), boron (B), cadmium (Cd), calcium (Ca), carbon (C), cerium (Ce), cobalt (Co), chromium (Cr), copper (Cu), germanium (Ge), hafnium (Hf), iron (Fe), lanthanum (La), lead (Pb), lithium (Li), magnesium (Mg), manganese (Mn), molybdenum (Mo), niobium (Nb), nickel (Ni), palladium (Pd), potassium (K), praseodymium (Pr), platinum (Pt), plutonium (Pu), samarium (Sm), selenium (Se), silicon (Si), sodium (Na), strontium (Sr), sulfur (S), tantalum (Ta), tellurium (Te), thorium (Th), tin (Sn), titanium (Ti), tungsten (W), uranium (U), vanadium (V), Yttrium (Y), zinc (Zn), and zirconium (Zr). ### Claim 5 (depends on 1) The method of claim 1, wherein the one or more pairs of reactive materials are selected from the group consisting of: aluminum (Al), copper (Cu), niobium (Nb), nickel (Ni), palladium (Pd), platinum (Pt), silicon (Si), and titanium (Ti). ### Claim 6 (depends on 1) The method of claim 1, wherein the multiple layer includes one or more barrier layers. ### Claim 7 (depends on 6) The method of claim 6, wherein each of the one or more barrier layers include one or more materials selected from the group consisting of: one or more transition metals, one or more transition metal oxides, one or more transition metal nitrides, and one or more aluminum oxides. ### Claim 8 (depends on 6) The method of claim 6, wherein each of the one or more barrier layers include one or more materials selected from the group consisting of: titanium (Ti); zirconium (Zr); hafnium (Hf); vanadium (V); niobium (Nb); tantalum (Ta); one or more oxides of Ti, Zr, Hf, V, Nb, and Ta; and one or more nitrides of Ti, Zr, Hf, V, Nb, and Ta. ### Claim 9 (depends on 1) The method of claim 1, wherein the multiple layer includes an insulating layer. ### Claim 10 (depends on 9) The method of claim 9, wherein the insulating layer is silicon dioxide. ### Claim 11 An integrated circuit (IC) comprising: a substrate; a front-end-of-the-line (FEOL) portion, wherein the FEOL portion rests on top of and in contact with the substrate; a memory level portion, wherein the memory level portion rests on top of and in contact with the FEOL portion; a back-end-of-the-line (BEOL) portion, wherein the BEOL portion rests on top of and in contact with the memory level portion; and a multiple layer that includes one or more pairs of reactive materials, wherein the multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate. ### Claim 12 (depends on 11) The IC of claim 11, wherein the one or more pairs of reactive materials are selected from the group consisting of: aluminum (Al), antimony (Sb), barium (Ba), beryllium (Be), bismuth (Bi), boron (B), cadmium (Cd), calcium (Ca), carbon (C), cerium (Ce), cobalt (Co), chromium (Cr), copper (Cu), germanium (Ge), hafnium (Hf), iron (Fe), lanthanum (La), lead (Pb), lithium (Li), magnesium (Mg), manganese (Mn), molybdenum (Mo), niobium (Nb), nickel (Ni), palladium (Pd), potassium (K), praseodymium (Pr), platinum (Pt), plutonium (Pu), samarium (Sm), selenium (Se), silicon (Si), sodium (Na), strontium (Sr), sulfur (S), tantalum (Ta), tellurium (Te), thorium (Th), tin (Sn), titanium (Ti), tungsten (W), uranium (U), vanadium (V), Yttrium (Y), zinc (Zn), and zirconium (Zr). ### Claim 13 (depends on 11) The IC of claim 11, wherein the one or more pairs of reactive materials are selected from the group consisting of: aluminum (Al), copper (Cu), niobium (Nb), nickel (Ni), palladium (Pd), platinum (Pt), silicon (Si), and titanium (Ti). ### Claim 14 (depends on 11) The IC of claim 11, wherein the multiple layer includes one or more barrier layers. ### Claim 15 (depends on 14) The IC of claim 14, wherein each of the one or more barrier layers include one or more materials selected from the group consisting of: one or more transition metals, one or more transition metal oxides, one or more transition metal nitrides, and one or more aluminum oxides. ### Claim 16 (depends on 14) The IC of claim 14, wherein each of the one or more barrier layers include one or more materials selected from the group consisting of: titanium (Ti); zirconium (Zr); hafnium (Hf); vanadium (V); niobium (Nb); tantalum (Ta); one or more oxides of Ti, Zr, Hf, V, Nb, and Ta; and one or more nitrides of Ti, Zr, Hf, V, Nb, and Ta. ### Claim 17 (depends on 11) The IC of claim 11, wherein the multiple layer includes an insulating layer. ### Claim 18 (depends on 17) The IC of claim 17, wherein the insulating layer is silicon dioxide.