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US 2018/0005938 A1Published application
Memory array structure and methods of fabricating thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.
Claims20
A memory device comprising:
- an array of memory cells;
- a first bit-line coupled to memory cells of a first column of the array of memory cells, wherein the first bit-line is disposed on a first metal layer;
- a second bit-line coupled to the first bit-line, wherein the second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via;
- and
- a word line coupled to a row of the array of memory cells.
2 more elements
A memory device comprising:
- an array of memory cells;
- a first bit-line coupled to memory cells of a first column of the array of memory cells, wherein the first bit-line is disposed on a first metal layer;
- a second bit-line coupled to the first bit-line, wherein the second bit-line is coupled to the first bit-line, wherein the second bit-line is disposed on a second metal layer above the first metal layer;
- a first complement bit-line coupled to memory cells of the first column of the array of memory cells, wherein the first complement bit-line is disposed on the first metal layer;
- a second complement bit-line coupled to the first complement bit-line, wherein the second complement bit-line is disposed on the second metal layer;
- and
- a word line coupled to a row of the array of memory cells.
4 more elements
A memory device comprising:
- a cell comprising:
- a pass-gate transistor;
- a first bit-line connected to a drain node of the pass-gate transistor;
- and
- a second bit-line connected to the first-bit line through a via, wherein one of the first and second bit-lines extends to a control circuitry for the memory device.
2 more elements
Dependencies are inferred from the claim text.