Enhanced self-alignment of vias for a semiconductor device

An integrated circuit comprising:

• a plurality of components formed in a front end of line process;
• one or more metal lines coupling two or more components to each other;
• and
• one or more vias arranged to couple together two metal lines;
• the vias formed by:
• providing a semiconductor wafer in which front end of line (FEOL) processing has been completed;
• depositing a dielectric layer over a metal layer;
• depositing a hard mask over the dielectric layer;
• forming a lithographic pattern over the hard mask, wherein the lithographic pattern contains lines with one or more notched areas;
• and
• etching a via in one of the one or more notched areas of the lithographic pattern.

A method of forming vias in a semiconductor, the method comprising:

• providing a semiconductor wafer in which front end of line (FEOL) processing has been completed;
• depositing a dielectric layer over a metal layer;
• depositing a hard mask over the dielectric layer;
• forming a lithographic pattern over the hard mask, wherein the lithographic pattern contains lines with one or more notched areas;
• and
• etching a via such that the via is located adjacent to one of the one or more notched areas of the lithographic pattern.