Semiconductor component and method of manufacture

A semiconductor component, comprising:

• a support structure having a top surface, a bottom surface, a mold compound between the top surface and the bottom surface, first, second, and third leads extending from a side, a die receiving structure in the mold compound, and an interconnect structure in the mold compound;
• an electrically insulating support having a first surface and a second surface, the second surface opposite the first surface and electrically coupled to the die receiving structure;
• a first semiconductor chip mounted to the second surface of the electrically insulating support, the first semiconductor chip having first and second surfaces, a first gate bond pad, a first source bond pad, and a first drain bond pad, the first semiconductor chip configured from a III-N semiconductor material, wherein the second surface of the first semiconductor chip is coupled to the electrically insulating substrate;
• and
• a second semiconductor chip mounted to the first semiconductor chip and having first and second surfaces, a second gate bond pad, a second source bond pad, and a second drain bond pad, the second semiconductor chip configured from a silicon based material, wherein the second surface of the second semiconductor chip is coupled to the first source bond pad.

A semiconductor component having at least a first terminal, comprising:

• a leadframe having first and second opposing sides and a first lead, the first lead integrally formed with the leadframe and a portion of the first side serving as a die receiving area and a second lead, wherein the second lead is electrically isolated from the leadframe;
• an electrically insulating support having a first surface and a second surface, the second surface opposite the first surface and electrically coupled to the die receiving area;
• a first semiconductor chip mounted to the die receiving area, the first semiconductor chip comprising a first substrate having a first surface and a second surface that serve as first and second surfaces of the first semiconductor chip, respectively, a first gate bond pad, a first source bond pad, and a first drain bond pad, the first semiconductor chip configured from a III-N semiconductor material, wherein the second surface of the first semiconductor chip is coupled to the first surface of the electrically insulating support;
• and
• a second semiconductor chip mounted to the first semiconductor chip and having first and second surfaces, the second semiconductor chip configured from a silicon based material, wherein the second surface of the second semiconductor chip is coupled to the first source bond pad.