Fabrication of a vertical fin field effect transistor with reduced dimensional variations
AssigneeInternational Business Machines Corporation
InventorKangguo Cheng
Life of this patent
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Abstract
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
Claims11
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, comprising:
- forming two dummy fin trenches in a substrate, wherein each of the two dummy fin trenches is on opposite sides of a portion of the substrate;
- forming a dummy fin fill in each of the two dummy fin trenches;
- forming a first dummy fin from one of the dummy fin fills, a second dummy fin from the other of the two dummy fin fills, and a vertical fin from the portion of the substrate between the two dummy fin trenches, wherein the first dummy fin and second dummy fin are border fins and the vertical fin is an interior fin;
- and
- removing the border fins.
11-20. (canceled)
Dependencies are inferred from the claim text.