Vertical fet devices with multiple channel lengths

A method for forming a semiconductor device, the method comprising:

• forming a first cavity and a second cavity in a semiconductor substrate;
• forming a first source/drain region in the first cavity and a second source/drain region in the second cavity;
• forming a bottom spacer on the first source/drain region and the second source/drain region;
• forming a first cavity in the bottom spacer that exposes a portion of the first source/drain region and forming a second cavity in the bottom spacer that exposes a portion of the second source/drain region;
• growing a first channel region in the first cavity and a second channel region in the second cavity;
• removing a portion of the bottom spacer to expose sidewalls of the first channel region and the second channel region;
• forming a first gate stack over the sidewalls of the first channel region and a second gate stack over the sidewalls of the second channel region;
• forming a gate conductor layer over exposed portions of the bottom spacer and around the first gate stack and the second gate stack;
• removing a portion of the gate conductor layer adjacent to the first gate stack;
• removing a portion of the gate conductor layer adjacent to the second gate stack such that the gate conductor has a first thickness adjacent to the first gate stack and a second thickness adjacent to the second gate stack, the first thickness is less than the second thickness;
• removing portions of the first gate stack and the second gate stack to expose portions of the first channel region and the second channel region;
• forming a sacrificial spacer over exposed portions of the first channel region and the second channel region;
• removing exposed portions of the gate conductor layer to expose portions of the bottom spacer;
• depositing a top spacer over the first gate stack and the second gate stack;
• removing exposed portions of the first channel region to form a cavity in the top spacer;
• and
• forming a third source/drain region in the cavity in the top spacer and the inter-level dielectric layer.

A method for forming a semiconductor device, the method comprising:

• forming a first source/drain region and a second source/drain region on a substrate;
• forming a first spacer layer on the first source/drain region and the second source/drain region;
• forming a first cavity in the first spacer layer that exposes a portion of the first source/drain region and forming a second cavity in the first spacer layer that exposes the second source/drain region;
• growing a first channel region in the first cavity and a second channel region in the second cavity;
• forming a gate stack layer on the first channel region and the second channel region;
• forming a gate conductor layer adjacent to the first gate stack and the second gate stack;
• recessing a portion of the gate conductor layer adjacent to the first channel region;
• forming a second spacer on the gate conductor layer;
• and
• forming a third source/drain region on the first channel region and a fourth source/drain region on the second channel region.

A method for forming a semiconductor device, the method comprising:

• forming a trench isolation region in a semiconductor substrate;
• forming a cavity in the substrate;
• forming a first source/drain region in the cavity;
• forming a layer of spacer material on the first source/drain region;
• forming a cavity in the layer of spacer material that exposes the first source/drain region;
• growing a channel region in the cavity;
• removing portions of the layer of spacer material to expose portions of the channel region;
• forming a gate stack on the channel region;
• depositing a gate conductor layer on the gate stack removing portions of the gate conductor layer to expose portions of the gate stack;
• removing exposed portions of the gate stack to expose portions of the channel region;
• depositing a second layer of spacer material over the channel region;
• removing portions of the channel region to form a cavity in the second layer of spacer material;
• and
• forming a second source/drain region in the cavity in the second layer of spacer material.

A semiconductor device comprising:

• a first source/drain region arranged on a semiconductor substrate;
• a second source/drain region arranged on the semiconductor substrate;
• a bottom spacer arranged on the first source/drain region;
• a bottom spacer arranged on the second source/drain region;
• a first gate stack having a first length arranged on the first source/drain region;
• a second gate stack having a second length arranged on the second source/drain region, the first length is shorter than the second length;
• a top spacer arranged on the first gate stack;
• and
• a top spacer arranged on the second gate stack.