Vertical transistor with variable gate length

A method of forming a vertical transistor, the method comprising:

• forming a first pair of fins on a substrate;
• forming a second pair of fins on the substrate;
• forming a first trench in the substrate and interposed between each one of the first pair of fins;
• forming a second trench in the substrate and interposed between each one of the second pair of fins, wherein the second trench is deeper than the first trench;
• forming a doped source or a doped drain at a base of the first trench in direct contact with the substrate;
• forming a doped source or a doped drain at a base of the second trench in direct contact with the substrate, wherein the doped source or the doped drain at the base of the second trench is deeper than the doped source or the doped drain at the base of the first trench;
• forming a first semiconductor structure interposed between each one of the first pair of fins, the first semiconductor structure having a first gate region interposed between a first source region and a first drain region;
• and
• forming a second semiconductor structure interposed between each one of the second pair of fins, the second semiconductor structure having a first gate region interposed between a second source region and a second drain region.