Integrated metal gate cmos devices

A method for forming semiconductor devices, the method comprising:

• forming a first channel region, a second channel region, a third channel region, and a fourth channel region on a substrate;
• forming a first metal layer on the first channel region, the second channel region, the third channel region, and the fourth channel region;
• forming a sacrificial block layer on the first metal layer and forming a sacrificial patterning layer on the sacrificial block layer;
• removing the first metal layer, the sacrificial block layer and the sacrificial patterning layer from the first channel region;
• forming a barrier metal layer on the first channel region and over a nitride layer along with forming the barrier metal layer on the second channel region, the third channel region, and the fourth channel region;
• removing, from the second channel region and the third channel region, the first metal layer, the sacrificial block layer, the sacrificial patterning layer, and the barrier metal layer;
• removing, from the fourth channel region, the barrier metal layer, and the sacrificial patterning layer;
• removing the sacrificial block layer from the fourth channel region;
• depositing a third metal layer and a work function metal layer on the first channel region, the second channel region, the third channel region, and the fourth channel region;
• removing the third metal layer and the work function metal layer from the third channel region;
• and
• depositing another work function metal on the first channel region, the second channel region, the third channel region, and the fourth channel region.