Contact structure and associated method for flash memory

A method for manufacturing a semiconductor device, comprising:

• providing a substrate structure including a semiconductor substrate having an active region, at least one gate structure on the active region and including a gate dielectric layer on the active region, a gate portion on the gate dielectric layer, and a hardmask on the gate;
• forming a first dielectric layer on the at least one gate structure and a surface of the active region adjacent to the at least one gate structure, wherein a portion of the first dielectric layer on the hardmask and the hardmask form a mask member;
• forming a second dielectric layer on the first dielectric layer covering the at least one gate structure;
• performing a surface treatment on the second dielectric layer so that an upper surface of the second dielectric layer is flush with an upper surface of the mask member and a first recess is formed in a middle portion of the upper surface of the mask member;
• forming a third dielectric layer on the second dielectric layer covering the mask member;
• and
• selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the mask member to form an opening adjacent to the at least one gate structure, the opening exposing a portion of the first dielectric layer on sidewalls of the at least one gate structure and a portion of the first dielectric layer on the active region adjacent to the at least one gate structure.