Booster circuit
AssigneeToshiba Memory Corporation
InventorTakeshi HIOKA
Life of this patent
Estimating the term…
Abstract
A booster circuit includes a charge pump circuit and a clock processing circuit. The clock processing circuit includes a first transistor of a first conductivity type, a second transistor of a second conductivity type, and a third transistor of a third conductivity type. The first and second transistors are connected in series between a high-voltage node and a low-voltage node, and gates of the first and second transistors are connected to each other. The third transistor is connected in parallel with the first transistor between the high-voltage node and an output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to the charge pump circuit.
Claims20
A booster circuit comprising:
- a charge pump circuit including a plurality of transistors connected in series in each of which a gate and a channel electrode are connected, and a plurality of capacitors each of which is connected to the channel electrode of a corresponding one of the transistors;
- and
- a clock processing circuit including
- a first transistor of a first conductivity type and a second transistor of a second conductivity type that are connected in series between a high-voltage node and a low-voltage node, gates of the first and second transistors being connected to each other, and
- a third transistor of the second conductivity type connected in parallel with the first transistor between the high-voltage node and a first output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to at least one of the capacitors of the charge pump circuit.
A semiconductor memory device comprising:
- a semiconductor memory cell array;
- and
- a peripheral circuit configured to control operation of the semiconductor memory cell array, the peripheral circuit including a booster circuit configured to generate voltages used for the operation, wherein
- the booster circuit includes:
- a charge pump circuit including a plurality of transistors connected in series in each of which a gate and a channel electrode are connected, and a plurality of capacitors each of which is connected to the channel electrode of a corresponding one of the transistors;
- and
- a clock processing circuit including
- a first transistor of a first conductivity type and a second transistor of a second conductivity type that are connected in series between a high-voltage node and a low-voltage node, gates of the first and second transistors being connected to each other, and
- a third transistor of the second conductivity type connected in parallel with the first transistor between the high-voltage node and a first output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to at least one of the capacitors of the charge pump circuit.
Dependencies are inferred from the claim text.