High voltage switching circuitry for a cross-point array
AssigneeUnity Semiconductor Corporation
InventorsChristophe Chevallier, Chang Hua Siau
Life of this patent
Estimating the term…
Abstract
A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.
Claims21
(canceled)
An integrated circuit comprising:
- a substrate;
- a base layer formed on the substrate, the base layer comprising a decoder formed with a plurality of transistors configured to operate within a first voltage range;
- and
- a cross-point memory array formed above the base layer, the cross-point memory array comprising:
- a plurality of conductive array lines;
- and
- a plurality of re-writable two-terminal memory cells formed at intersections of the plurality of conductive array lines, the plurality of re-writable two-terminal memory cells configured to operate within a second voltage range, wherein the first voltage range is smaller than the second voltage range.
A memory device comprising:
- a base layer comprising a decoder formed with a plurality of transistors configured to operate within a first voltage range;
- and
- a plurality of memory layers formed above the base layer, each of the memory layers comprising a separate cross-point memory array, each cross-point memory array comprising:
- a plurality of conductive array lines;
- and
- a plurality of re-writable two-terminal memory cells formed at intersections of the plurality of conductive array lines, the plurality of re-writable two-terminal memory cells configured to operate within a second voltage range, wherein the first voltage range is smaller than the second voltage range.
A system comprising:
- a processing device;
- and
- a memory device coupled to the processing device, the memory device comprising:
- a base layer comprising a decoder formed with a plurality of transistors configured to operate within a first voltage range;
- and
- a plurality of memory layers formed above the base layer, each of the memory layers comprising a separate cross-point memory array, each cross-point memory array comprising:
- a plurality of conductive array lines;
- and
- a plurality of re-writable two-terminal memory cells formed at intersections of the plurality of conductive array lines, the plurality of re-writable two-terminal memory cells configured to operate within a second voltage range, wherein the first voltage range is smaller than the second voltage range.
Dependencies are inferred from the claim text.