Memory cell, memory device, and electronic device having the same

A memory device, comprising:

• a memory cell that stores a single bit;
• a word line connected to the memory cell;
• a bit line connected to the memory cell;
• a complementary bit line connected to the memory cell;
• an auxiliary bit line;
• an auxiliary complementary bit line;
• and
• a switch circuit, wherein the switch circuit electrically connects the auxiliary bit line to the bit line during a write operation, electrically connects the auxiliary complementary bit line to the complementary bit line during the write operation, electrically disconnects the auxiliary bit line from the bit line during a read operation, and electrically disconnects the auxiliary complementary bit line from the complementary bit line during the read operation.

A memory device, comprising:

• a memory cell array comprising a plurality of memory cells;
• a plurality of word lines connected to the plurality of memory cells;
• a plurality of bit lines connected to the plurality of memory cells;
• a plurality of complementary bit lines connected to the plurality of memory cells;
• a plurality of auxiliary bit lines;
• a plurality of auxiliary complementary bit lines;
• and
• a switch circuit, wherein the switch circuit electrically connects the plurality of auxiliary bit lines to the plurality of bit lines in response to receiving a write signal having a first value indicating a write operation, electrically connects the plurality of auxiliary complementary bit lines to the plurality of complementary bit lines in response to receiving the write signal having the first value indicating the write operation, electrically disconnects the plurality of auxiliary bit lines from the plurality of bit lines in response to receiving the write signal having a second value indicating a read operation, and electrically disconnects the plurality of auxiliary complementary bit lines from the plurality of complementary bit lines in response to receiving the write signal having the second value indicating the read operation.

A memory device, comprising:

• a memory cell that stores a single bit;
• a word line connected to the memory cell;
• a bit line connected to the memory cell;
• a complementary bit line connected to the memory cell;
• an auxiliary bit line;
• an auxiliary complementary bit line;
• a first switch connected between the bit line and the auxiliary bit line, wherein the first switch electrically connects the auxiliary bit line to the bit line in response to receiving a write signal having a first value indicating a write operation, and electrically disconnects the auxiliary bit line from the bit line in response to receiving the write signal having a second value indicating a read operation;
• and
• a second switch connected between the complementary bit line and the auxiliary complementary bit line, wherein the second switch electrically connects the auxiliary complementary bit line to the complementary bit line in response to receiving the write signal having the first value indicating the write operation, and electrically disconnects the auxiliary complementary bit line from the complementary bit line in response to receiving the write signal having the second value indicating the read operation.