Dram and access and operating method thereof
AssigneeMediatek Inc.
InventorBo-Wei HSIEH
Life of this patent
Estimating the term…
Abstract
An operating method for a dynamic random access memory (DRAM) obtains a plurality of first sub-commands of a first activate command via a command bus, and obtaining a plurality of first address information regarding a plurality of first portions of a first row address of a specific bank via an address bus. Each of the first sub-commands corresponds to an individual first portion of the first row address of the specific bank. The method further combines the first portions of the first row address of the specific bank in response to a specific sub-command of the first sub-commands, so as to obtain a first complete row address; and obtains an access command via the command bus.
Claims10
An operating method for a dynamic random access memory (DRAM), comprising:
- obtaining a plurality of first sub-commands of a first activate command via a command bus, and obtaining a plurality of first address information regarding a plurality of first portions of a first row address of a specific bank via an address bus, wherein each of the first sub-commands corresponds to an individual first portion of the first row address of the specific bank;
- combining the first portions of the first row address of the specific bank in response to a specific sub-command of the first sub-commands, so as to obtain a first complete row address;
- and
- obtaining an access command via the command bus.
A dynamic random access memory (DRAM), comprising:
- an address combination circuit, comprising:
- a control unit, providing a bank address and a trigger signal according to address information from a controller via an address bus;
- a first selector, storing a portion of a row address of the address information into a storage unit according to the bank address;
- and
- a second selector, providing a complete row address from the storage unit according to the bank address and the trigger signal;
- a column address decoder, obtaining a column address from the controller via the address bus according to an access command from the controller via the command bus,
- wherein when the access command is a write command, first data from the controller via a data bus is received and stored according to the complete row address and the column address, and
- when the access command is a read command, second data corresponding to the complete row address and the column address is provided to the controller via the data bus.
Dependencies are inferred from the claim text.