Methods of operating semiconductor memory devices and semiconductor memory devices

A semiconductor memory device comprising:

• a plurality of pads disposed on a substrate;
• a memory cell array configured to store data which is synchronized with a differential data clock signal received from an external memory controller in a write operation of the semiconductor memory device;
• a control logic circuit configured to control access on the memory cell array in response to a command and address received from the memory controller;
• and
• an input/output (I/O) circuit configured to transmit read data from the memory cell array to the memory controller with a selected one of a first strobe signal generated based on a frequency-divided data clock signal from which the differential data clock signal is divided and a differential strobe signal generated based on the frequency-divided data clock signal and having the first strobe signal and a second strobe signal which is the first strobe signal inverted,
• wherein the control logic circuit is configured to select between the first strobe signal and the differential strobe signal, and
• wherein the semiconductor memory device does not include a dedicated strobe pad among the plurality of pads.

A method of operating a semiconductor memory device including a memory cell array and a plurality of chip pads on a substrate, the method comprising:

• transmitting data from the memory cell array to an outside of the semiconductor memory device through a data pad of the chip pads in a first mode of the semiconductor memory device;
• transmitting a data strobe (RDQS) signal to the outside of the semiconductor memory device through a first pad of the chip pads in a second mode of the semiconductor memory device;
• and
• transmitting a differential strobe signal including the RDQS signal and an inverted data strobe (RDQSB) signal to the outside of the semiconductor memory device through the first pad and a second pad of the chip pads, in a third mode of the semiconductor memory device,
• wherein the semiconductor memory device does not include a dedicated data strobe pad among the plurality of chip pads.