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US 2018/0005685 A1Published application
Semiconductor device comprising charge pump circuit for generating substrate bias voltage
AssigneeRenesas Electronics Corporation
InventorTakumi HASEGAWA
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Abstract
In a semiconductor device, a substrate voltage generation circuit includes frequency-dividing/multiplying circuits for dividing or multiplying a frequency of a clock signal, and charge pump circuits configured to be operative in accordance with clock signals having divided or multiplied frequencies to generate substrate bias voltages. The frequency-dividing/multiplying circuits have a frequency-dividing/multiplying rate variable by a command issued from a processing circuit.
Claims14
A semiconductor device comprising:
- a semiconductor integrated circuit including a processing circuit;
- and
- a substrate voltage generation circuit for generating a substrate bias voltage supplied to at least one of transistors configuring the semiconductor integrated circuit,
- wherein the substrate voltage generation circuit includes:
- a frequency-dividing/multiplying circuit configured to output a frequency-divided/multiplied signal, a frequency of the frequency-divided/multiplied signal being equal to a frequency of a first clock signal divided or multiplied by a frequency-dividing/multiplying rate indicated by the processing circuit;
- and
- a charge pump circuit configured to operate in accordance with the first clock signal divided or multiplied by the frequency-dividing/multiplying circuit, and
- wherein a boost voltage output from the charge pump circuit is supplied to the semiconductor integrated circuit as the substrate bias voltage.
5 more elements
A semiconductor device comprising:
- a semiconductor integrated circuit including a processing circuit;
- a first substrate voltage generation circuit for generating a first substrate bias voltage supplied to at least one of PMOS (Positive-channel Metal Oxide Semiconductor) transistors configuring the semiconductor integrated circuit;
- and
- a second substrate voltage generation circuit for generating a second substrate bias voltage supplied to at least one of NMOS (Negative-channel Metal Oxide Semiconductor) transistors configuring the semiconductor integrated circuit,
- wherein the first substrate voltage generation circuit includes:
- a first frequency-dividing/multiplying circuit configured to output a first frequency-divided/multiplied signal, a frequency of the first frequency-divided/multiplied signal being equal to a frequency of a first clock signal divided or multiplied by a first frequency-dividing/multiplying rate indicated by the processing circuit;
- and
- a first charge pump circuit configured to operate in accordance with the first clock signal divided or multiplied by the first frequency-dividing/multiplying circuit,
- wherein the second substrate voltage generation circuit includes:
- a second frequency-dividing/multiplying circuit configured to output a second frequency-divided/multiplied signal, a frequency of the second frequency-divided/multiplied signal being equal to a frequency of the first clock signal divided or multiplied by a second frequency-dividing/multiplying rate indicated by the processing circuit;
- and
- a second charge pump circuit configured to operate in accordance with the first clock signal divided or multiplied by the second frequency-dividing/multiplying circuit,
- wherein a boost voltage output from the first charge pump circuit is supplied to the semiconductor integrated circuit as the first substrate bias voltage, and
- wherein a boost voltage output from the second charge pump circuit is supplied to the semiconductor integrated circuit as the second substrate bias voltage.
11 more elements
Dependencies are inferred from the claim text.