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US 2018/0005676 A1Published application
Memory cell unit and recurrent neural network including multiple memory cell units
AssigneesSamsung Electronics Co., Ltd., Universitaet Zuerich
InventorsDaniel NEIL, Shih-Chii LIU, Michael PFEIFFER
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Abstract
A memory cell unit and a recurrent neural network including memory cell units are provided. The memory cell unit includes a first time gate configured to control a cell state value of the memory cell unit, based on a phase signal of an oscillatory frequency, and a second time gate configured to control an output value of the memory cell unit, based on the phase signal.
Claims21
A memory cell unit comprising:
- a first time gate configured to control a cell state value of the memory cell unit, based on a phase signal of an oscillatory frequency;
- and
- a second time gate configured to control an output value of the memory cell unit, based on the phase signal.
A recurrent neural network comprising:
- an input layer;
- a hidden layer comprising memory cell units, each of the memory cell units comprising:
- a first time gate configured to control a cell state value of a respective one of the memory cell units, based on a phase signal of an oscillatory frequency;
- and
- a second time gate configured to control an output value of the respective one of the memory cell units, based on the phase signal;
- and
- an output layer.
4 more elements
A memory cell unit comprising:
- an input gate configured to determine a degree to which an input value of the memory cell unit is reflected;
- a first memory configured to store a first cell state value of the memory cell unit;
- a forget gate configured to determine a degree to which the first cell state value of the memory cell unit is forgotten;
- a second memory configured to store a second cell state value of the memory cell unit, based on the determined degree to which the input value is reflected and the determined degree to which the first cell state value is forgotten;
- a first time gate configured to maintain the first cell state value, and update the first cell state value to be the second cell state value, based on a phase signal;
- an output gate configured to determine a degree to which the first cell state value is output;
- and
- a second time gate configured to, based on the phase signal, maintain an output value of the memory cell unit, and update, based on the first cell state value and the determined degree to which the first cell state value is output, the output value.
5 more elements
Dependencies are inferred from the claim text.