Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

A system for dual mode power saving in a stacked circuit topology having logic preservation, comprising:

• a memory;
• a processor being coupled to a memory;
• a pre-charge circuit for pre-charging a global bitline to enable switching of the global bitline;
• a sleep mode control circuit for providing a signal to disable an array of circuit elements and switch a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit;
• a keeper circuit coupled to the global bitline;
• the logic function circuit coupled to a solar bitline;
• and
• an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit, wherein the logic function circuit comprises at least two stacked transistors to pull-up the solar bitline based on a received signal from the sleep mode control circuit, wherein the two stacked transistors are p-type field-effect transistors (PFET), wherein the two stacked transistors are smaller than the effective pull-up transistor.