Hybrid lpddr4-dram with cached nvm and flash-nand in multi-chip packages for mobile devices

An apparatus comprising:

• a hybrid-memory package including:
• a non-volatile memory (NVM);
• a dynamic random access memory (DRAM), wherein a portion of the DRAM is allocated as a cache memory for the NVM;
• and
• a hybrid controller for the NVM and DRAM including:
• an NVM interface to the NVM;
• a DRAM interface to the cache memory;
• a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM, and includes a DMA chip select line activated by the processor when the parallel data bus is available, wherein the hybrid controller is configured to, in response to activation of the DMA chip select line, perform DMA cache data transfers including one or more of a DRAM preload, an update of one or more pages of NVM, and a read or write of cache metadata;
• and
• logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.

An apparatus comprising:

• a hybrid-memory package including:
• a non-volatile memory (NVM);
• a dynamic random access memory (DRAM), wherein a portion of the DRAM is allocated as a cache memory for the NVM;
• and
• a hybrid controller for the NVM and DRAM including:
• an NVM interface to the NVM;
• a DRAM interface to the cache memory;
• a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM, wherein the host interface of the hybrid controller includes an acknowledge/interrupt (ACK/IRQ) line and the hybrid controller is configured to communicate status of an NVM transfer operation to the host processor using pulse modulation of a signal on the ACK/IRQ line;
• and
• logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.

An apparatus comprising:

• a hybrid-memory package including:
• a non-volatile memory (NVM);
• a dynamic random access memory (DRAM, wherein a portion of the DRAM is allocated as a cache memory for the NVM, wherein the cache memory includes multiple cache memory pages;
• and
• a hybrid controller for the NVM and DRAM including:
• an NVM interface to the NVM;
• a DRAM interface to the cache memory;
• a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM;
• and
• logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM, wherein the hybrid controller is configured to address a cache memory page by truncating a specified number of higher order address bits of the NVM memory received via the host interface.