Apparatuses and methods for performing logical operations using sensing circuitry
AssigneeMicron Technology, Inc.
InventorGlen E. Hush
Life of this patent
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Abstract
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation.
Claims21
-20. (canceled)
An apparatus, comprising:
- an array of memory cells;
- and
- sensing circuitry coupled to the array, and comprising:
- a plurality of sense amplifiers coupled to respective pairs of complementary sense lines;
- and
- a plurality of compute components coupled to the sense amplifiers via respective pairs of pass gates coupled to the respective pairs of complementary sense lines;
- and
- wherein the plurality of compute components comprise respective stages of a shift register into which data values on the respective pairs of complementary sense lines are loaded by enabling the respective pairs of pass gates.
A method, comprising:
- loading a first data value, from a sense amplifier, to a compute component of sensing circuitry coupled to an array of memory cells via a pair of complementary sense lines, wherein the compute component is coupled to the sense amplifier via a pair of pass transistors;
- shifting the first data value, from the compute component, to an adjacent compute component corresponding to an adjacent column of memory cells;
- and
- shifting a second data value, from a different adjacent compute component corresponding to a different adjacent column of memory cells, to the compute component;
A system, comprising:
- a memory device comprising;
- a plurality of columns of memory cells coupled to sensing circuitry comprising respective sense amplifiers and corresponding compute components coupled to respective complementary sense line pairs;
- and
- a controller configured to operate the plurality of compute components as a loadable shift register by:
- causing loading of data values into respective compute components via control signals provided to gates of respective pass transistor pairs coupling the respective sense amplifiers and corresponding compute components;
- causing shifting of the loaded data values to at least one of an adjacent compute component in a first direction and an adjacent compute component in a second direction.
Dependencies are inferred from the claim text.