US 2018/0005668 A1Published application

Semiconductor device and method for operating the semiconductor device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsYutaka SHIONOIRI, Tomoaki ATSUMI, Kiyoshi KATO, Takanori MATSUZAKI

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Abstract

To provide a semiconductor device with a high output voltage. A gate of a first transistor is electrically connected to a first terminal through a first capacitor. A gate of a second transistor is electrically connected to a second terminal through a second capacitor. One of a source and a drain of a third transistor is electrically connected to the gate of the first transistor through a third capacitor. One of a source and a drain of a fourth transistor is electrically connected to the gate of the second transistor through a fourth capacitor. The other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to a high potential power source. A third terminal is electrically connected to one of a source and a drain of the second transistor.

Claims14

Dependent claims

A semiconductor device comprising:

a comparator comprising a first transistor to a seventh transistor, a first capacitor to a fourth capacitor, a first input terminal, a second input terminal, and an output terminal;
an eighth transistor and a ninth transistor each comprising a front gate and a back gate;
and
a fifth capacitor,
wherein a gate of the first transistor is electrically connected to the first input terminal through the first capacitor,
wherein a gate of the second transistor is electrically connected to the second input terminal through the second capacitor,
wherein one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor through the third capacitor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the second transistor through the fourth capacitor,
wherein the other of the source and the drain of the third transistor, the other of the source and the drain of the fourth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor are electrically connected to a high potential power source,
wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a low potential power source,
wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein the other of the source and the drain of the second transistor and the other of the source and the drain of the seventh transistor are electrically connected to the output terminal, and
wherein the first input terminal is electrically connected to the back gate of the eighth transistor, the front gate and the back gate of the ninth transistor, one of a source and a drain of the ninth transistor, and one electrode of the fifth capacitor.

11 more elements

A method for operating a semiconductor device,

the semiconductor device comprising a first transistor to a seventh transistor, a first capacitor to a fourth capacitor, a first input terminal, a second input terminal, and an output terminal,
wherein a gate of the first transistor is electrically connected to the first input terminal through the first capacitor,
wherein a gate of the second transistor is electrically connected to the second input terminal through the second capacitor,
wherein one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor through the third capacitor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the second transistor through the fourth capacitor,
wherein the other of the source and the drain of the third transistor, the other of the source and the drain of the fourth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor are electrically connected to a high potential power source,
wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a low potential power source,
wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the sixth transistor, and
wherein the other of the source and the drain of the second transistor and the other of the source and the drain of the seventh transistor are electrically connected to the output terminal,
the method for operating the semiconductor device comprising:
applying a first potential to the gate of the first transistor;
applying a second potential to the gate of the second transistor;
applying a third potential to the first input terminal, wherein the third potential is a negative potential;
applying a fourth potential to the gate of the first transistor, wherein the fourth potential is a positive potential;
applying a fifth potential to the second input terminal, wherein the fifth potential is a negative potential;
applying a sixth potential to the gate of the second transistor, wherein the sixth potential is a positive potential;
and
outputting a seventh potential from the output terminal, wherein the seventh potential corresponds to a difference between the fourth potential and the sixth potential,
wherein the first potential is higher than the fourth potential, and
wherein the second potential is higher than the sixth potential.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/626,595Filed 19 Jun 2017
Priority: JP 2016-13065030 Jun 2016
Published: 4 Jan 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification26 codes

G11C 5/06
Details of stores covered by group G11C11/00: arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 11/403
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: with charge regeneration common to a multiplicity of memory cells,…