Method and apparatus for dynamic mode memory testing

An electronic device, comprising:

• a clock divider configured to divide a frequency of a clock based on a selected BIST mode;
• a built-in self-test (BIST) controller in communication with the clock divider;
• a memory in communication with the BIST controller and the clock divider;
• a dynamic memory test module in communication with the clock divider, BIST controller, and memory;
• and
• a low voltage test access port in communication with the BIST controller for receiving test outputs from the BIST controller and providing test data output.

An apparatus comprising:

• means for resetting an electronic device containing a memory to be tested;
• means for selecting a built-in self-test (BIST) mode;
• means for inputting the selected BIST mode to a BIST apparatus;
• means for performing the selected BIST mode and recording test results;
• means for selecting an additional BIST mode;
• and
• means for switching to the additional BIST mode immediately after completion of the first BIST mode.

A non-transitory computer-readable medium, containing instructions, which when executed cause a processor to perform the following steps:

• resetting an electronic device containing a memory to be tested;
• selecting a built-in self-test (BIST) mode;
• inputting the selected BIST mode to a BIST apparatus;
• performing the selected BIST mode and recording test results;
• selecting an additional BIST mode;
• and
• switching to the additional BIST mode immediately after completion of the selected BIST mode.