Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register

A machine readable storage medium containing program code that when processed by an image processor comprising a two dimensional execution lane array and a two dimensional shift register array causes the image processor to perform a method, comprising:

• repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.

A machine readable storage medium containing program code that when processed by a processing unit causes a method to be performed, comprising:

• articulating a method in a higher level program code that accesses data with memory read and write instructions having an instruction format that specifies a memory location in x,y coordinates, the higher level program code to be compiled into object code that is executable on an image processor having a two dimensional execution lane array and a two dimensional shift register array, the object code to cause the image processor to:
• double a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration;
• execute one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations.

A machine readable storage medium containing program code that when processed by a processing unit causes a method to be performed, comprising:

• articulating a method in a higher level program code that accesses data with memory read and write instructions having an instruction format that specifies a memory location in x,y coordinates, the higher level program code to be compiled into object code that is executable on an image processor having a two dimensional execution lane array and a two dimensional shift register array, the object code to cause the image processor to:
• repeatedly execute one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.